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datasheet 552-02s april 18, 2017 1 ?2017 integrated device technology, inc. low skew 2-input mux and 1 to 8 clock buffer 552-02s description the 552-02s is a low skew, single -input to eight- output clock buffer. the device offers a dual input with pin select for switching between two clock sources. it has best in class additive phase jitter of sub 50fsec idt makes many non-pll and pll based low skew output devices as well as zero delay buffers to synchronize clocks. contact us for all of your clocking needs. features low rms additive phase jitter: 50fs low output skew: 50ps operating voltages of 1.8v to 3.3v packaged in 16-pin tssop and 16-pin vfqfn, pb-free input clock multiplexer si mplifies clock selection output enable pin tri-states outputs input/output clock frequency up to 200 mhz low power cmos technology 3.3v tolerant inputs extended temperature (-40c to +105c) block diagram oe q3 q4 q2 q5 q6 q1 q0 q7 ina inb 10 sela
low skew 2-input mux and 1 to 8 clock buffer 2 april 18, 2017 552-02s datasheet pin assignments input source select pin descriptions external components a minimum number of external components are required for proper operation. decoupling capacitors of 0.01 ?? f should be connected between vdd on pin 2 and gnd on pin 7, and betwee n vdd on pin 15 and gnd on pi n 10, as close to the device as possible. a 33 ? series terminating resistor should be used on each clock output if the trace is longer than 1 inch. to achieve the low output skews that the 552-02s is capable of, careful attention must be paid to board layou t. essentially, al l 8 outputs must have identical termi nations, identical loads, and identical trace geometries. if they do not, the output skew will be degraded. for example, using a 30 ?? series termination on one output (with 33 ? on the others) will cause at least 15ps of skew. sela input 0i n b 1i n a pin number pin name pin type pin description 1 oe input output enable. tri-states outputs when low. internal pull-up resistor. 2 vdd power connect to +1.8v, +2.5v or +3 .3v. must be the same as pin 15. 3 q0 output clock output 0. 4 q1 output clock output 1. 5 q2 output clock output 2. 6 q3 output clock output 3. 7 gnd power connect to ground. 8 inb input clock input b. 3.3v tolerant. 9 ina input clock input a. 3.3v tolerant. 10 gnd power connect to ground. 11 q4 output clock output 4. 12 q5 output clock output 5. 13 q6 output clock output 6. 14 q7 output clock output 7. 15 vdd power connect to +1.8v, +2.5v or +3.3v. must be the same as pin 2. 16 sela input selects either ina or inb. internal pull-up resistor. 12 1 11 2 10 3 9 oe 4 vdd 5 q0 6 vdd 7 q1 8 q2 q7q6 q5 q3 q4 ina gnd gnd 1615 14 13 inb sela 16 pin tssop 1 16-pin vfqfn 5 9 13 oe vdd q0 q1 q2q3 gnd inb q7 q6 sela vdd q5q4 gnd ina 2 3 4 678 10 11 12 14 15 16
april 18, 2017 3 low skew 2-input mux and 1 to 8 clock buffer 552-02s datasheet absolute maximum ratings stresses above the ratings listed below ca n cause permanent damage to the 552-02s. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. function al operation of the device at these or any other conditions above those indicated in the operational sections of the specif ications is not implied. exposur e to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 3.465v all inputs and outputs -0.5 v to 3.465v ambient operating temperatur e, extended -40 to +105c storage temperature -65 to +150 ? c junction temperature 175 ? c soldering temperature 260 ? c parameter min. typ. max. units ambient operating temper ature, extended -40 C +105 ? c power supply voltage (measured in respect to gnd) +1.71 +3.465 v
low skew 2-input mux and 1 to 8 clock buffer 4 april 18, 2017 552-02s datasheet dc electrical characteristics vdd=1.8 v 5% , ambient temperature -40c to +105c, unless stated otherwise vdd=2.5 v 5% , ambient temperature -40c to +105c, unless stated otherwise vdd=3.3 v 5% , ambient temperature -40c to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 1.71 1.89 v input high voltage, ina, inb v ih note 1 0.7xvdd 1.89 v input low voltage, ina, inb v il note 1 0.3xvdd v input high voltage, oe, sela v ih 0.7xvdd vdd v input low voltage, oe, sela v il 0.3xvdd v output high voltage v oh i oh = -10 ma 1.3 v output low voltage v ol i ol = 10 ma 0.35 v operating supply current idd no load, 135 mhz 32 ma parameter symbol conditions min. typ. max. units operating voltage vdd 2.375 2.625 v input high voltage, ina, inb v ih note 1 0.7xvdd 2.625 v input low voltage, ina, inb v il note 1 0.3xvdd v input high voltage, oe, sela v ih 0.7xvdd vdd v input low voltage, oe, sela v il 0.3xvdd v output high voltage v oh i oh = -16 ma 1.8 v output low voltage v ol i ol = 16 ma 0.5 v operating supply current idd no load, 135 mhz 43 ma parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.465 v input high voltage, ina, inb v ih note 1 0.7xvdd 3.465 v input low voltage, ina, inb v il note 1 0.3xvdd v input high voltage, oe, sela v ih 0.7xvdd vdd v input low voltage, oe, sela v il 0.3xvdd v output high voltage v oh i oh = -25 ma 2.2 v output low voltage v ol i oh = 25 ma 0.7 v operating supply current idd no load, 135 mhz 55 ma
april 18, 2017 5 low skew 2-input mux and 1 to 8 clock buffer 552-02s datasheet ac electrical characteristics vdd = 1.8v 5% , ambient temperature -40c to +105c, unless stated otherwise vdd = 2.5v 5% , ambient temperature -40c to +105c, unless stated otherwise vdd = 3.3v 5% , ambient temperature -40c to +105c, unless stated otherwise notes: 1. with rail-to-rail input clock. 2. between any two outputs with equal loading. 3. propagation delay matching through the part. 4. duty cycle on outputs will match incoming clock duty c ycle. consult idt for tight duty cycle clock generators. parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.36 to 1.44 v, c l =5 pf 1 1.5 ns output fall time t of 1.44 to 0.36 v, c l =5 pf 1 1.5 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2m s propagation delay note 1 135mhz 2 2.5 3 ns buffer additive phase jitter, rms 125mhz , integration range: 12khz-20mhz 50 65 ps output to output skew note 2 rising edges at vdd/2 0 65 ps input a to input b skew note 3 0 50 ps parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.5 to 2.0 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.0 to 0.5 v, c l =5 pf 0.6 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2m s propagation delay note 1 135mhz 2 2.7 3.5 ns buffer additive phase jitter, rms 125mhz , integration range: 12khz-20mhz 50 65 ps output to output skew note 2 rising edges at vdd/2 0 65 ps input a to input b skew note 3 0 50 ps parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.66 to 2.64 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.64 to 0.66 v, c l =5 pf 0.6 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2m s propagation delay note 1 135mhz 2 2.5 3 ns buffer additive phase jitter, rms 125mhz , integration range: 12khz-20mhz 50 65 ps output to output skew note 2 rising edges at vdd/2 0 65 ps input a to input b skew note 3 0 50 ps
low skew 2-input mux and 1 to 8 clock buffer 6 april 18, 2017 552-02s datasheet package outline and dimensions (16-pin vfqfn)
april 18, 2017 7 low skew 2-input mux and 1 to 8 clock buffer 552-02s datasheet package outline and dimensions, cont. (16-pin vfqfn)
low skew 2-input mux and 1 to 8 clock buffer 8 april 18, 2017 552-02s datasheet package outline and dimensions (16-pin tssop)
april 18, 2017 9 low skew 2-input mux and 1 to 8 clock buffer 552-02s datasheet package outline and dimensions (16-pin tssop), cont.
low skew 2-input mux and 1 to 8 clock buffer 10 april 18, 2017 552-02s datasheet package outline and dimensions (16-pin tssop), cont.
april 18, 2017 11 low skew 2-inpu t mux and 1 to 8 clock buffer 552-02s datasheet ordering information g after the two-letter package code denotes pb-free configuration, rohs compliant. marking diagrams notes: 1. ** is the lot sequence. 2. yyww or y is the last digit(s) of the year and week that the part was assembled. 3. $ denotes the mark code. 4. lot denotes lot number. 5. g after the two-letter package code denotes rohs compliant package. 6. i denotes extended temperature range device. 7. bottom marking: country of origin (tssop only). revision history part / order number marking shippi ng packaging package temperature 552-02spggi tbd tubes 16-pin tssop -40c to +105c 552-02spggi8 tape and reel 16-pin tssop -40c to +105c 552-02scmgi tubes 16-pin vfqfn -40c to +105c 552-02scmgi8 tape and reel 16-pin vfqfn -40c to +105c rev. date originator description of change b 04/18/17 c.p. 1. replaced package outline drawi ngs with latest cmg16 and pgg16 versions. 2. updated legal disclaimer. a 07/11/16 h.g. release to final. 02si y** 16-pin qfn idt552-0 2spggi yyww$ 16-pin tssop lot
disclaimer integrated device technology, inc. (idt) and its affiliated companies (her ein referred to as idt) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idts sole discretion. performance specifications and operating parame ters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without represen tation or warranty of any kind, wh ether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warra nty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at th eir o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidia ries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, vi sit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support 552-02s april 18, 2017 12 ?2017 integrated device technology, inc.

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